`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/08/27 15:07:18
// Design Name: 
// Module Name: sim_and_gate
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sim_and_gate(
    );
reg A;
reg B;
wire Y;

and_gate u1(A,B,Y);

initial begin
    A=0;B=0;
    #10
    A=1;B=0;
    #10
    A=1;B=1;
    #10
    A=0;B=1;
    #10
    A=0;B=0;
end

endmodule
